April 10, 2020

Computer Speeds – Computerphile



2Ghz ≠ 2Ghz – Well sometimes! Dr Steve Bagley on why the clock cycles of a CPU aren’t enough to measure it’s speed.

https://www.facebook.com/computerphile

This video was filmed and edited by Sean Riley.

Computer Science at the University of Nottingham: https://bit.ly/nottscomputer

Computerphile is a sister project to Brady Haran’s Numberphile. More at http://www.bradyharan.com

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31 thoughts on “Computer Speeds – Computerphile

  1. I could listen to Dr. Bagley talk about this for hours. It's really important and we are now at a point where we literally can't make processors better just by speaking in terms of clock cycles alone. We require entirely new ideas about processor architecture, because the x86 model is done.

  2. THz computer will be achievable if you get the compute elements down to being a collection of atoms, and the bus wiring to be single carbon or metal nanotubes, a single atom in diameter.

  3. No mention of SIMD vectorization or multicore as a design strategy to mitigate the frequency limit (a 24 core CPU with AVX512 instruction set and 2 FMA units can in theory do 768 double precision floating point operations every clock cycle). No mention of the power and thermal limit that restrict clock frequencies.

  4. Fact of the matter is, regarding General Purpose Use – Clock speed has had a larger factor in quantifiable CPU throughput than 'design' has – looking all he way back to 8Mhz 286's.
    Little things like MMS (remember that?) added little bits – AES-NI is a massive thing – but these are additional ASIC style development really. For the most part – the software you run isn't scaled / compiled well for the architecture capabilities of the CPU you are running on.
    UNLESS it's dedicated simulation.

  5. Why are youtube's auto-subs not enabled for this? Is this intentionally disabled by you or did YT didn't get a chance to process it for that yet or… how does that work?

  6. The GHz is how fast the little legs move. But some of the runners can carry more, some go through short cuts… some have longer distance to cover. 😛

  7. Is it reasonable to assume that there's an inverse relationship between clock speed and number of logical gates activated per pipeline stage? My understanding has been that there's generally no magical frequency limit but that we could in theory split a pipeline into so many simple stages that it can run at like 10ghz+ while utilizing the same process to build (assuming such a clock can be accurately generated).

  8. A nice analogy I like to show is with engines/motors, the clock speed is the RPM, but the key is that the torque is also important, and that "torque" is defined by the architecture, which is where most of the improvements happen between architectures.

    It starts to fail down when you want to consider instructions which take different times, I still think it's helpful as a quick analogy. 🙂

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